1. Field of the Invention
The present invention relates to a method and an apparatus for adjusting an output bit rate of a video packet so that a bit rate desired by a user can be efficiently and precisely achieved when Transport Streams (TSs) of a Moving Picture Experts Group (MPEG)-2 system are output by the packet.
2. Description of the Related Art
Recently, digital video data transmission through a broadband communication system, such as a cable TV network or a satellite TV network, has been popularized via satellite/terrestrial/cable transmission media. Generally, compression technology is applied to source video/audio data of digital broadcasting, etc., to service large data quantities. To this end, MPEG compression technology, including an MPEG-1, an MPEG-2, an MPEG-4, etc., is widely applied.
In a transport layer, an MPEG-2 TS is used, which is a standard TS made for MPEG-2 transmission. Herein, a TS may be transmitted at a proper Constant Bit Rate (CBR) or a Variable Bit Rate (VBR).
A conventional method of adjusting an output bit rate of a video packet may include: (1) “Implementation of a New MPEG-2 Transport Stream Processor for Digital Television Broadcasting, IEEE TRANSACTIONS ON BROADCASTING, VOL, 48, NO. 4, DECEMBER 2002”; and (2) “Implementation of MPEG-2 Transport Stream Remultiplexer for DTV Broadcasting, IEEE Transactions on Consumer Electronics, Vol, 48, No. 2, MAY 2002”.
According to technology (1) of the conventional method, it is possible to change the bit rate of output video from 1.5 to 120 Mbps in the transmission of an MPEG-2 TS video packet, but this is determined by external clocks such as two external clocks “Clock 1/Clock 2” as illustrated in FIG. 1a. In such a case, it is necessary to separately install an external variable clock source in order to change a clock, which results in inefficiency. Such a problem also occurs in technology (2) of the conventional method. In technology (2), an output interface clock is generated using a separate Direct Digital Synthesizer (DDS) chip “AD9860” as illustrated in FIG. 1b. Further, it is necessary to provide peripheral circuits including a clock source, such as a crystal oscillator “XTAL OSC” for an output interface, separately from a clock for operating an MPEG-2 TS packet processing logic, a DDS chip for generating a new clock by using the clock source, a low-pass filter, etc. In addition, it is necessary to connect data buses from a processor in order to control the DDS chip, thus the circuit becomes complicated. Moreover, in order to change a clock during an operation, an output interface must be initialized. Therefore, data may be lost.